Virtual Address Space & Memory Isolation Questions
Virtual address space concepts, address translation, paging/segmentation, page tables, TLBs, page fault handling, and memory protection mechanisms that isolate processes from each other. Includes hardware support (MMU), virtual memory management policies, and implications for security and performance.
HardTechnical
74 practiced
A production C service shows intermittent SIGSEGV crashes at different user-space addresses. As the primary SRE, provide a prioritized debugging plan: what to collect immediately (core dumps, configs), which tools to run (gdb, addr2line, valgrind, ASAN), kernel settings to adjust (ulimit, core_pattern, ptrace_scope), and how to preserve evidence without disrupting traffic.
HardTechnical
73 practiced
Write pseudocode in C for a minimal page-fault handler in a toy kernel (not production kernel). The handler should: read faulting address, check permission vs VMA-like structure, allocate a physical page, zero it, insert/update the PTE, and resume the faulting thread. Identify race conditions and points where locks or TLB flushes are needed.
MediumTechnical
68 practiced
Given this excerpt from /proc/<pid>/smaps (simplified):Name: /usr/bin/appSize: 1024 kBRss: 256 kBPss: 128 kBPrivate_Clean: 128 kBPrivate_Dirty: 64 kBShared_Clean: 64 kBExplain which parts indicate private heap growth vs shared mappings, and how you'd use smaps over time to detect a memory leak in the process.
HardTechnical
113 practiced
Implement a user-space TLB simulator in Python. Input: a trace file of virtual page numbers (one VPN per line), TLB size (entries), associativity (1 for fully associative), and page size. Output: total accesses and TLB miss rate. Describe complexity and how you'd validate the simulator with small traces.
MediumTechnical
62 practiced
Compare transparent hugepages (THP) and explicit hugepages allocation. For a database workload with large in-memory working set, explain when to use THP vs pre-allocated hugepages and outline a staged testing plan to validate performance improvements.
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